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The direction of the quadrature code and control of the counter is generated by the simple binary function
outlined by Table 22.1 (p. 312) . Note that this function also filters some invalid inputs that may occur
when the shaft changes direction or temporarily toggles direction.
Table 22.1. PCNT QUAD Mode Counter Control Function
Inputs
Control/Status
S1IN posedge
0
0
1
1
S1IN negedge
0
1
0
1
Count Enable
0
1
1
0
CNTDIR status bit
0
0
1
0
Note
PCNTn_S1IN is sampled on both edges of PCNTn_S0IN.
22.3.2 Register Access
The counter-clock domain may be clocked externally. To update the counter-clock domain registers
from software in this mode, 2-3 clock pulses on the external clock are needed to synchronize accesses
to the externally clocked domain. Clock source switching is controlled from the registers in the CMU
(Chapter 11 (p. 92) ).
When the RSTEN bit in the PCNTn_CTRL register is set to 1, the PCNT clock domain is asynchronously
held in reset. The reset is synchronously released two PCNT clock edges after the RSTEN bit in the
PCNTn_CTRL register is cleared by software. This asynchronous reset restores the reset values in
PCNTn_TOP, PCNTn_CNT and other control registers in the PCNT clock domain.
Since this module is a Low Energy Peripheral, and runs off a clock which is asynchronous to
the HFCORECLK, special considerations must be taken when accessing registers. Please refer to
Section 5.3 (p. 18) for a description on how to perform register accesses to Low Energy Peripherals.
Note
PCNTn_TOP and PCNTn_CNT are read-only registers. When writing to PCNTn_TOPB,
make sure that the counter value, PCNTn_CNT, can not exceed the value written to
PCNTn_TOPB within two clock cycles.
22.3.3 Clock Sources
The 32 kHz LFACLK is one of two possible clock sources. The clock select register is described in
Chapter 11 (p. 92) . The default clock source is the LFACLK.
This PCNT module may also use PCNTn_S0IN as an external clock to clock the counter
(EXTCLKSINGLE mode) and to sample PCNTn_S1IN (EXTCLKQUAD mode). Setup, hold and max
frequency constraints for PCNTn_S0IN and PCNTn_S1IN for these modes are specified in the device
datasheet.
To use this module, the LE interface clock must be enabled in CMU_HFCORECLKEN0, in addition to
the module clock.
Note
PCNT Clock Domain Reset, RSTEN, should be set when changing clock source for PCNT.
If changing to an external clock source, the clock pin has to be enabled as input prior to
2011-04-12 - d0001_Rev1.10
312
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